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 Monday, November 3, 2003

EE398/498 VLSI Design Through VHDL

 

INSTRUCTOR: Dr. David Carey

CONTACT INFO: david.carey@wilkes.edu

OFF. HRS: SLC-221 by appointment (email and I will make accommodations)

CLASS TIME: Wednesday 6:00-8:45PM, SLC-223

 

Objective: Functional verification is one of the most complex and expensive tasks in the current system-on-chip (SOC) design methodology. Various studies have shown that the verification consumes more than 70% of the total design cost (time). The goal of this course is to develop a comprehensive understanding of the technologies behind hardware verification. The students will develop an appreciation of the existing capabilities and limitations of various hardware modeling and verification methods. The course will cover the basics of modeling and simulation using VHDL, and hardware verification using formal techniques such as symbolic simulation, model checking, theorem proving, satisfiability solving, and equivalence checking. The lectures will also cover case studies of verifying complex systems including verification of Intel microprocessors.

Course Outline: Tentative course outline is shown below.

      1.      Introduction to Hardware Modeling

·        Reading

·         The Ten Commandments of Excellent Design by Peter Chambers

2.      Hardware Modeling using Verilog

·      Reading

·         Handbook on Verilog HDL by Daniel Hyde

3.      Hardware Modeling using VHDL

·        Reading

·         The Designer's Guide to VHDL by Peter J. Ashenden

4.      Hardware Simulation

            ·        Reading

·         Architecture description languages for programmable embedded systems

·         A Universal Technique for Fast and Flexible Instruction Set Architecture Simulation

·         Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation

·         An Efficient Retargetable Framework for Instruction-Set Simulation

·         Memory Access Optimizations in Instruction-Set Simulators

5.      Binary Decision Diagrams

·         Reading

·         Graph-Based Algorithms for Boolean Function Manipulation by Randal E. Bryant

6.      Project Plan.

7.      Model Checking

·        Reading

·        Model Checking by Edmund Clarke, Orna Grumberg, and D. Long.

8.      Symbolic Simulation

9.      Equivalence Checking

10.  Satisfiability Solvers

11.  Theorem Proving

12.  Manufacturing Testing

·        Reading

·         Design for Test Methodology Case Study for Motorola C-5e DCP Using the Cadence Incisive Accelerator/Emulator by Justin Hernandez

      13. Final Project Due

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 Thursday, October 2, 2003

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